Typical digital circuit designs involve a high level of integration along with high data transmission rate requirements in the order of gigabytes per second, which necessitate an accurate timing analysis of the digital system. Timing analyses usually involve determining and accounting for delays present within the circuit design. To determine delays, measurements can be made on test circuits or models to determine delays of individual standard cells or logic gates within a programmable chip, for example.
Signal delays due to logic gates are due to switching times of transistors that comprise the logic gates. The switching times may be due to process variations in a semiconducting material on which the logic gate is fabricated. Typically, integrated circuits are produced in large batches on a single wafer of electronic-grade silicon (EGS) through processes such as photolithography. The wafer is cut into many pieces, each containing one copy of the circuit and each of these pieces is called a die. There are two types of process variations; inter-die or die-to-die variations (global), and intra-die or within-die variations (local).
Many techniques exist for measuring a delay of components of a circuit. For example, a Picosecond Imaging Circuit Analysis (PICA) can be used to obtain quantitative delay information from circuits. A very weak picosecond pulse of light is emitted by each field effect transistor (FET) in a complementary metal oxide semiconductor (CMOS) circuit whenever the circuit changes logic state. The pulsed emission can be imaged by counting a number of infra-red photons from a back side of the package chip. With a suitable imaging detector, PICA allows time resolved measurement on devices. However, the technique requires infra-red measurement ability, which makes the technique costly and tedious.
Another technique that may be used is a delay measurement based on delay lock loop (DLL) configuration to change a phase of a clock signal to enhance clock rise-to-data output valid timing characteristics. However, the complexity of the DLL configuration for an on-chip measurement circuitry solution limits its large scale implementation which may be needed for characterizing process variations.
Normally, the delay of a standard circuit component is quite small, and the delay can be amplified by cascading a number of circuit stages so that the delay of the individual cell is determined by averaging. However, it may be difficult to extract gate to gate delay variations from simple cascaded circuits, and modified or complicated cascaded circuitry is usually not a part of any standard cell library. Hence, this approach may not be suitable for delay mismatch measurement of standard cell library.